As electronic products continue to progress, designs of integrated circuits are developed towards trends of higher density, faster operating speed and lower power consumption to meet market demands. As a result, critical dimension of semiconductor elements are constantly reduced by following the Moore's law. However, the miniaturization process of conventional transistors encounters various challenges, e.g., a short-channel effect. As a channel of a transistor becoming shorter, a threshold voltage (Vth) is decreased to lead to issues of an increased leakage current and increased power consumption.
To mitigate negative effects of the short-channel effect, a variety of transistors have been developed. Among the transistors, a tunneling transistor is the most prominent one. In the US Patent Publication No. 20120153263, it disclosed when a tunneling field-effect transistor in an OFF state, a drain voltage (Vd) is positive and a gate voltage (Vg) is substantially zero. That is, in such OFF state, electrons do not pass through an intrinsic channel between a source and the drain. When the transistor is in an ON state, the drain voltage (Vd) and the gate voltage (Vg) are both positive. That is, in such ON state, electrons pass through the intrinsic channel between the source and the drain. As a bandgap of the intrinsic channel (Bc) is transferred due to the gate voltage (Vg) is higher with respect to a bandgap of source (Bs), electrons are allow to flow. Accordingly, the tunneling field-effect transistor has a larger ON/OFF current compared to a conventional metal-oxide semiconductor field-effect transistor (MOSFET).
However, in order to implement a lower OFF current, the tunneling field-effect transistor cannot obtain a larger ON current. Therefore, a solution for overcoming such issue is needed.